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CY25200
Programmable Spread Spectrum Clock Generator for EMI Reduction
Features
* Wide operating output (SSCLK) frequency range -- 3-200 MHz * Programmable spread spectrum with nominal 31.5-kHz modulation frequency. * Center spread: 0.25% to 2.5% * Down spread: -0.5% to -5.0% * Input frequency range: -- External crystal: 8-30 MHz fundamental crystals -- External reference: 8-166 MHz Clock * Integrated phase-locked loop (PLL) * Programmable crystal load capacitor tuning array * Low cycle-to-cycle Jitter * 3.3V operation with 2.5V output clock drive option * Spread spectrum On/Off function * Power-down or Output Enable function * Output frequency select option
Benefits
* Suitable for most PC peripherals, networking, and consumer applications. * Provides wide range of spread percentages for maximum EMI reduction, to meet regulatory agency Electro Magnetic Compliance (EMC) requirements. Reduces development and manufacturing costs and time-to-market. * Eliminates the need for expensive and difficult to use higher order crystals. * Internal PLL generates up to 200 MHz outputs, and can generate custom frequencies from an external crystal or a driven source. * Enables fine-tuning of output clock frequency by adjusting CLoad of the crystal. Eliminates the need for external CLoad capacitors. * Application compatibility in standard and low-power systems. * Provides ability to enable or disable spread spectrum with an external pin. * Enables low-power state or output clocks to High-Z state.
Logic Block Diagram
7
Divider Bank 1 Output Select Matrix VCO P Divider Bank 2 SSCLK1
8 SSCLK2 9
SSCLK3
XIN/CLKIN 1 XOUT 16 CXOUT
OSC. CXIN
Q
12 SSCLK4
PLL
14 SSCLK5/REFOUT/CP2 15 SSCLK6/REFOUT/CP3
2
3
AVDD
5
AVSS
13
VSS
11
VDDL
6
VSSL
4
CP0
10
CP1
Pin Configuration
VDD
XIN VDD AVDD CP0 AVSS VSSL SSCLK1 SSCLK2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
XOUT SSCLK6/REFOUT/CP3 SSCLK5/REFOUT/CP2 VSS SSCLK4 VDDL CP1 SSCLK3
Cypress Semiconductor Corporation Document #: 38-07633 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised April 22, 2004
CY25200
General Description
The CY25200 is a Spread Spectrum Clock Generator (SSCG) IC used for the purpose of reducing Electro Magnetic Interference (EMI) found in today's high-speed digital electronic systems. The device uses a Cypress proprietary Phase-Locked Loop (PLL) and Spread Spectrum Clock (SSC) technology to synthesize and modulate the frequency of the input clock. By frequency modulating the clock, the measured EMI at the fundamental and harmonic frequencies are greatly reduced. This reduction in radiated energy can significantly reduce the cost of complying with regulatory agency requirements (EMC) and improve time to market without degrading system performance. The CY25200 uses a factory-programmable configuration memory array to synthesize output frequency, spread %, crystal load capacitor, clock control pins, PD# and OE options. The spread % is factory programmed to either center spread or down spread with various spread percentages. The range for center spread is from 0.25% to 2.50%. The range for down spread is from -0.5% to -5.0%. Contact the factory for smaller or larger spread % amounts if required. The input to the CY25200 can be either a crystal or a clock signal. The input frequency range for crystals is 8-30 MHz, and for clock signals is 8-166 MHz. The CY25200 has six clock outputs, SSCLK1 to SSCLK6. The frequency modulated SSCLK outputs can be programmed from 3-200 MHz. The CY25200 products are available in a 16-pin TSSOP package with a commercial operating temperature range of 0 to 70C.
CY25200 Pin Summary
Name XIN XOUT VDD AVDD VSS AVSS VDDL VSSL SSCLK1 SSCLK2 SSCLK3 SSCLK4 SSCLK5/REFOUT/CP2 SSCLK6/REFOUT/CP3 CP0[1] CP1[1] Pin Number 1 16 2 3 13 5 11 6 7 8 9 12 14 15 4 10 Description Crystal Input or Reference Clock Input. Crystal Output. Leave this pin floating if external clock is used. 3.3V Power supply for digital logic and SSCLK5/6 clock drives. 3.3V analog-PLL power supply Ground Analog ground 2.5V or 3.3V power supply for SSCLK1/2/3/4 clock drives VDDL power supply ground Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V) Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V) Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V) Programmable Spread Spectrum Clock Output at VDDL Level (2.5V or 3.3V) Programmable Spread Spectrum Clock or Buffered Reference Output at VDD Level (3.3V) or Control pin, CP2 Programmable Spread Spectrum Clock or Buffered Reference Output at VDD Level (3.3V) or Control pin, CP3 Control Pin 0 Control Pin 1
Note: 1. Pins can be programmed to be any of the following control signals: OE: Output Enable, OE = 1 all the SSCLK outputs are enabled, PD#: Powerdown, PD# = 0, all the SSCLK outputs are three-stated and the part enters a low-power state, SSON: Spread Spectrum Control (SSON = 0, No Spread and SSON = 1, Spread Signal), CLKSEL: SSCLK Output Frequency Select. Please see page 3 for control pins programming option.
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CY25200
Table 1. Fixed Function Pins Pin Function Pin Name Pin# Units Program Value CLKSEL = 0 Program Value CLKSEL = 1 Output Clock Functions and Frequency SSCLK1 7 MHz ENTER DATA ENTER DATA SSCLK2 8 MHz ENTER DATA ENTER DATA SSCLK3 9 MHz ENTER DATA ENTER DATA SSCLK4 12 MHz ENTER DATA ENTER DATA Input Frequency XIN and XOUT 1 and 16 MHz CXIN and CXOUT XIN and XOUT 1 and 16 pF Spread Percent SSCLK[1:6] Frequency Modulation SSCLK[1:6]
7,8,9,12,14,15 7,8,9,12,14,15 % kHz
ENTER DATA
ENTER DATA
ENTER DATA
31.5
Table 2. Multi-function Pins Pin Function Pin Name Pin# Units Program Value CLKSEL = 0 Program Value CLKSEL = 1 Output Clock /REFOUT /OE/SSON/CLKSEL SSCLK5/REFOUT/CP2 14 MHz ENTER DATA ENTER DATA SSCLK6/REFOUT/CP3 15 MHz ENTER DATA ENTER DATA ENTER DATA ENTER DATA OE/PD#/SSON/CLKSEL CP0 4 N/A CP1 10 N/A
Programming Description
Customers planning to use the CY25200 need to provide the programming information described as "ENTER DATA" in Table 1 and Table 2, then should contact local Cypress Sales. Additional information on the CY25200 can be obtained from the Cypress web site at www.cypress.com.
* Output Enable (OE), if OE = 1, all the SSCLK or REFOUT outputs are enabled * SSON, Spread spectrum control, 1 = spread on and 0 = spread off * CLKSEL, SSCLK output frequency select * PD#, Active Low, PD# = 0, all the outputs are three-stated and the part enters a low-power state * The last control signal is the Power down (PD#) that can be implemented only through programming CP0 or CP1 (CP2 and CP3 can not be programmed as PD#). Here is an example with 3 control pins, * CLKIN = 33MHz * SSCLK1/2/3/4 = 100MHz with 1% Spread * SSCLK 5 = REFOUT(33MHz) * CP0 (Pin 4) = PD# * CP1 (Pin 10) = OE * CP3 (pin 15) = SSON The pinout for the above example is shown in Figure 1.
NC
SSON REFOUT(33.0MHz)
Product Functions
Control Pins (CP0, CP1, CP2 and CP3) There are four control signals available through programming of pins 4, 10, 14 and 15. CP0 (pin 4) and CP1 (pin10) are specifically designed to function as control pins. However pins 14 (SSCLK5/REFOUT/CP2) and 15 (SSCLK6/REFOUT/CP3) are multi-functional and can be programmed to be a control signal or an output clock (SSCLK or REFOUT). All of the control pins, CP0, CP1, CP2 and CP3 are programmable and can be programmed to have only one of the following functions:
33.0MHz VDD AVDD PD# AVSS VSSL 100MHz 100MHz
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VSS 100MHz VDDL OE 100MHz
Figure 1.
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CY25200
The CLKSEL control pin enables the user to change the output frequency from one frequency (e.g., frequency A) to another frequency (e.g., frequency B). These must be related frequencies that can be derived off of a common VCO frequency, e.g., 33.333 MHz and 66.666 MHz can both be derived from a VCO = 400 MHz and dividing it down by 12 and 6 respectively. Table 3 shows an example of how this can be implemented. The VCO frequency range is 100-400MHz. The CY25200 has two separate dividers, Divider 1 and Divider 2, these two can be loaded to have any number between 2 and 130 providing two different but related frequencies as explained above. In the above example SSCLK5 (pin 14) and SSCLK6(pin 15) are used as output clocks, however they could have been used as control signals. See Figure 2 for the pinout. Input Frequency (XIN, pin 1 and XOUT, pin 16) The input to the CY25200 can be a crystal or a clock. The input frequency range for crystals is 8 to 30 MHz, and for clock signal is 8 to 166 MHz. CXIN and CXOUT (pin 1 and pin 16) The load capacitors at pin 1 (CXIN) and pin 16 (CXOUT) can be programmed from 12 pF to 60 pF with 0.5-pF increments. The programmed value of these on-chip crystal load capacitors are the same (XIN = XOUT = 12 to 60 pF). The required values of CXIN and CXOUT for matching crystal load (CL) can be calculated using the following formula: CXIN = CXOUT = 2CL - CP Where CL is the crystal load capacitor as specified by the crystal manufacturer and CP is the parasitic PCB capacitance. Table 3. Using Clock Select, CLKSEL Control Pin Input Freq. (MHz) 14.318 CLKSEL (Pin 4) CLKSEL = 0 CLKSEL = 1 SSCLK1 (Pin 7) 33.33 66.66 SSCLK2 (Pin 8) 33.33 66.66 SSCLK3 (Pin 9) 33.33 66.66 SSCLK4 (Pin 12) 33.33 66.66 REFOUT (Pin 14) 14.318 14.318 REFOUT (Pin 15) 14.318 14.318 For example, if a fundamental 16-MHz crystal with CL of 16 pF is used and CP is 2 pF, CXIN and CXOUT can be calculated as: CXIN = CXOUT = (2 x 16) - 2 = 30 pF. If using a driven reference clock, set CXIN and CXOUT to the minimum value 12 pF. Output Frequency (SSCLK1 through SSCLK6 Outputs) All of the SSCLK outputs are produced by synthesizing the input reference frequency using a PLL and modulating the VCO frequency. SSCLK[1:4] can be programmed to be only output clocks (SSCLK). SSCLK5 and SSCLK6 can also be programmed to function the same as SSCLK[1:4] or a buffered copy of the input reference (REFOUT) or they can be programmed to be a control pin as discussed in the control pins section. To utilize the 2.5V output drive option on SSCLK[1:4], VDDL must be connected to a 2.5V power supply (SSCLK[1:4] outputs are powered by VDDL). When using the 2.5V output drive option, the maximum output frequency on SSCLK[1:4] is 166MHz. Spread Percentage (SSCLK1 through SSCLK6 Outputs) The SSCLK frequency can be programmed at any percentage value from 0.25% to 2.5% for Center Spread and from -0.5% to -5.0% Down Spread. Frequency Modulation The frequency modulation is programmed at 31.5 kHz for all SSCLK frequencies from 3 to 200 MHz. Contact the factory if a higher modulation frequency is required.
14.318MHz VDD AVDD CLKSEL AVSS VSSL 33.33/66.66MHz 33.33/66.66MHz
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
XOUT
REFOUT(14.318MHz) REFOUT(14.318MHz)
VSS 33.33/66.66MHz VDDL SSON 33.33/66.66MHz
Figure 2. Table 3 Configuration Pinout
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CY25200
Switching Waveforms
Duty Cycle Timing (DC = t1A/t1B)
OUTPUT t1A t1B
Output Rise/Fall Time (SSCLK and REFCLK)
VDD 0V
Tr Tf Output Rise time (Tr) = (0.6 x VDD)/SR1 (or SR3) Output Fall time (Tf) = (0.6 x VDD)/SR2 (or SR4) Refer to AC Electrical Characteristics table for SR (Slew Rate) values.
OUTPUT
Power-down Timing and Power-up Timing
POWERDOWN VDD 0V VIL VIH tPU
(Asynchronous)
SSCLK tSTP
High Impedance
Output Enable/Disable Timing
OUTPUT ENABLE VDD 0V VIL VIH TOE2
(Asynchronous)
SSCLK TOE1
High Impedance
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CY25200
Informational Graphs [2]
172.5 171.5 170.5 169.5 168.5 167.5 166.5 165.5 164.5 163.5 162.5 161.5 160.5 159.5
0 20 40 60 80 100 120 Time (us) 140 160 180 200
Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= -4%
Fnominal
169.5 169 168.5 168 167.5 167 166.5 166 165.5 165 164.5 164 163.5 163 162.5
0 20
Spread Spectrum Profile: Fnom=166MHz, Fmod=30kHz, Spread%= +/-1%
Fnominal
40
60
80
100 120 Time (us)
140
160
180
200
68.5 68 67.5 67 66.5 66 65.5 65 64.5 64 63.5
0 20
Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= -4%
67.5 67 66.5
Fnominal
Spread Spectrum Profile: Fnom=66MHz, Fmod=30kHz, Spread%= +/-1%
66 65.5 65 64.5
Fnominal
40
60
80
100 120 Time (us)
140
160
180
200
0
20
40
60
80
100 120 Time (us)
140
160
180
200
Note: 2. The "Informational Graphs" are meant to convey the typical performance levels. No performance specifications is implied or guaranteed. Refer to the tables on pages 4 and 5 for device specifications.
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CY25200
Absolute Maximum Rating
Supply Voltage (VDD) .......................................-0.5 to +7.0V DC Input Voltage...................................... -0.5V to VDD + 0.5 Storage Temperature (Non-condensing)..... -55C to +125C Junction Temperature ................................ -40C to +125C Data Retention @ Tj = 125C............................... > 10 Years Package Power Dissipation...................................... 350 mW Static Discharge Voltage.......................................... > 2000V (per MIL-STD-883, Method 3015) Comments Parallel resonance, fundamental mode, AT cut Internal load caps Fundamental mode 3 0.5 2 mW Min. Typ. Max. Unit 8 6 30 30 25 MHz pF
Recommended Crystal Specifications
Parameter FNOM CLNOM R1 R3/R1 DL Description Nominal Crystal Frequency Nominal Load Capacitance Equivalent Series Resistance (ESR)
Ratio of Third Overtone Mode ESR to Ratio used because typical R1 values are much Fundamental Mode ESR less than the maximum spec Crystal Drive Level No external series resistor assumed
Recommended Operating Conditions
Parameter VDD VDDLHI VDDLLO TAC CLOAD CLOAD FSSCLK-HighVoltage FSSCLK-LowVoltage REFOUT fREF1 fREF2 tPU Description Operating Voltage Operating Voltage Operating Voltage Ambient Commercial Temp Max. Load Capacitance VDD/VDDL = 3.3V Max. Load Capacitance VDDL = 2.5V SSCLK1/2/3/4/5/6 when VDD = AVDD = VDDL = 3.3 V SSCLK5/6 when VDD = 3.3.V and VDDL = 2.5V REFOUT when VDD = AVDD = 3.3.V and VDDL = 3.3V or 2.5V Clock Input Crystal Input Power-up time for all VDDs to reach minimum specified voltage (power ramps must be monotonic) Min. 3.135 3.135 2.375 0 - - 3 3 8 8 8 0.05 Typ. 3.3 3.3 2.5 - - - - - - - - - Max. 3.465 3.465 2.625 70 15 15 200 166 166 166 30 500 Unit V V V C pF pF MHz MHz MHz MHz MHz ms
DC Electrical Specifications
Parameter[4] IOH3.3 IOL3.3 IOH2.5 IOL2.5 VIH VIL IVDD[5] IVDDL2.5[5] IVDDL3.3[5] IDDS IOHZ IOLZ Name Output High Current Output Low Current Output High Current Output Low Current Input High Voltage Input Low Voltage Supply Current Supply Current Supply Current Power-Down Current Output Leakage Description VOH = VDD - 0.5V, VDD/VDDL = 3.3V VOL = 0.5V, VDD/VDDL = 3.3V VOH = VDDL - 0.5V, VDDL = 2.5V VOL = 0.5V, VDDL = 2.5V CMOS levels, 70% of VDD CMOS levels, 30% of VDD AVDD/VDD Current VDDL Current (VDDL = 2.625V) VDDL Current (VDDL = 3.465V) VDD = VDDL = AVDD = 3.465V VDD = VDDL = AVDD = 3.465V Min. 10 10 8 8 0.7 0 - - - - - Typ. 12 12 16 16 - - - - - - - Max. - - - - 1.0 0.3 33 20 26 50 10 Unit mA mA mA mA VDD VDD mA mA mA uA uA
Notes: 3. Rated for 10 years. 4. Not 100% tested, guaranteed by design. 5. IVDD currents specified for SSCLK1/2/3/4/5/6 = 33.33 MHz with CLKIN = 14.318 MHz and 15 pF on all the output clocks.
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CY25200
AC Electrical Specifications
Parameter DC Description Output Duty Cycle Output Duty Cycle SR1 SR2 SR3 SR4 SR5 SR6 TCCJ1 Condition SSCLK, Measured at VDD/2 REFCLK, Measured at VDD/2 Duty Cycle of CLKIN = 50%. Min. 45 40 0.6 0.8 0.5 0.6 0.6 1.0 - - - - - - - - - - - - - - - - - - - 30.0 Typ. 50 50 - - - - - - - - - - - - - - - - - - - - - - 150 150 150 31.5 Max. Unit 55 60 2.0 3.5 2.2 3.0 1.9 2.9 110 170 140 290 100 120 180 180 110 170 190 330 90 110 160 150 300 300 300 33.0 ns ns ns kHz ps ps ps ps ps ps ps ps ps % % V/ns V/ns V/ns V/ns V/ns V/ns ps ps ps
Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 3.3V Rising/Falling Edge Slew Rate SSCLK1/2/3/4 100 MHz, VDD = VDDL = 3.3V Rising/Falling Edge Slew Rate SSCLK1/2/3/4 < 100 MHz, VDD = VDDL = 2.5V Rising/Falling Edge Slew Rate SSCLK1/2/3/4 100 MHz, VDD = VDDL = 2.5V Rising/Falling Edge Slew Rate SSCLK5/6 < 100 MHz, VDD = VDDL = 3.3V Rising/Falling Edge Slew Rate SSCLK5/6 100 MHz, VDD = VDDL = 3.3V Cycle-to-Cycle Jitter SSCLK1/2/3/4 CLKIN = SSCLK1/2/3/4 = 166MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 66.66 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 33.33 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 14.318MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
TCCJ2
Cycle-to-Cycle Jitter SSCLK5/6=REFOUT
CLKIN = SSCLK1/2/3/4 = 166 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 66.66 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 33.33 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V CLKIN = SSCLK1/2/3/4 = 14.318 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = VDDL = 3.3V
TCCJ3
Cycle-to-Cycle Jitter SSCLK1/2/3/4
CLKIN = SSCLK1/2/3/4 = 166 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 66.66MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 33.33 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 14.318 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
TCCJ4
Cycle-to-Cycle Jitter SSCLK5/6=REFOUT
CLKIN = SSCLK1/2/3/4 = 166 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 66.66 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 33.33 MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V CLKIN = SSCLK1/2/3/4 = 14.318MHz, 2% spread and SSCLK5/6 = REFOUT, VDD = 3.3V, VDDL = 2.5V
tSTP TOE1 TOE2 FMOD
Power-down Time (pin3 = PD#) Output Disable Time (pin3 = OE) Output Enable Time (pin3 = OE)
Time from falling edge on PD# to stopped outputs (Asynchronous) Time from falling edge on OE to stopped outputs (Asynchronous) Time from rising edge on OE to outputs at a valid frequency (Asynchronous)
Spread Spectrum Modulation SSCLK1/2/3/4/5/6 Frequency
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CY25200
AC Electrical Specifications (continued)
Parameter tPU1 tPU2 Description Power-up Time, Crystal is used Power-up Time, Reference clock is used Condition Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Time from rising edge on PD# to outputs at valid frequency (Asynchronous) Min. - - Typ. 3 2 Max. Unit 5 3 ms ms
Ordering Information
Ordering Code[6] CY25200ZXC_XXXW CY25200ZXC_XXXWT Package Type 16-lead TSSOP (Lead Free) 16-lead TSSOP- Tape and Reel (Lead Free) Temperature Operating Range Commercial, 0 to 70C Commercial, 0 to 70C
16-lead TSSOP Package Characteristics
Parameter Name theta JA Value 115 Unit C/W
JA
Notes: 6. "XXX" denotes the assigned product dash number. "W" denotes the different revisions of the product.
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CY25200
Package Drawing and Dimension
16-lead TSSOP 4.40 MM Body Z16.173
PIN 1 ID
1
DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153
6.25[0.246] 6.50[0.256] 4.30[0.169] 4.50[0.177]
PACKAGE WEIGHT 0.05gms
16
0.65[0.025] BSC.
0.19[0.007] 0.30[0.012]
1.10[0.043] MAX.
0.25[0.010] BSC GAUGE PLANE 0-8
0.076[0.003] 0.85[0.033] 0.95[0.037] 4.90[0.193] 5.10[0.200] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008]
51-85091-*A
All products and company names mentioned in this document may be the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY25200
Document History Page
Document Title: CY25200 Programmable Spread Spectrum Clock Generator for EMI Reduction Document Number: 38-07633 REV. ** *A ECN NO. 204243 220043 Issue Date See ECN See ECN Orig. of Change RGL RGL Description of Change New Data Sheet Minor Change: Corrected letter assignment in the ordering info for Lead Free.
Document #: 38-07633 Rev. *A
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